SPI - Serial Peripheral Interface

Example available on GitHub. Check liteboard SPI example.

SPI is a full-duplex, master - slave, synchronous serial interface used mainly used in embedded systems.

<uml> ditaa

/————–\ /—————\

SPI master SPI slave 1
SCLK +———–*——>+ SCLK
MOSI +———*-——>+ MOSI
MISO +←—–*--——-+ MISO
SS1 +——---——>+ SS
cGRE SS2 +—–\ cYEL

\————–/ | | | | 

                   | | | |       /---------------\  
                   | | | |       |  SPI slave 2  |
                   | | | |       |               |
                   | | | \------>+ SCLK          |
                   | | \-------->+ MOSI          |
                   | \-----------+ MISO          |
                   \------------>+ SS            |
                                 |         cYEL  |
                                 \---------------/

</uml>

Interface

  • SCLK - Serial Clock,
  • MOSI - Master Output Slave Input,
  • MISO - Master Input Slave Output,
  • SS - Slave Select

SPI configuration

To configure SPI interface following parameters must be defined:

  • clock frequency,
  • clock polarity (CPOL):
    • CPOL=0 - 0 is idle state, 1 is active state,
    • CPOL=1 - 0 is active state, 1 is idle state,
  • clock phase (CPHA):
    • CPHA=0 - data sampling on the first clock edge,
    • CPHA=1 - data sampling on the second clock edge.

liteSOM and SPI

ECSPI block diagram

ECSPI block diagram (source: i.MX 6UltraLite Applications Processor Reference Manual)

i.MX6UL supports up to four Enhanced Configurable Serial Peripheral Interfaces (ECSPI).

Each ECSPI contains a 64 x 32 receive buffer and a 64 x 32 transmit buffer. With data FIFOs, the ECSPI allows rapid data communication with fewer software interrupts.

Key features of the ECSPI include:

  • Full-duplex synchronous serial interface,
  • Master/Slave configurable,
  • Four Chip Select (SS) signals to support multiple peripherals,
  • Transfer continuation function allows unlimited length data transfers,
  • 32-bit wide by 64-entry FIFO for both transmit and receive data,
  • Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable,
  • Direct Memory Access (DMA) support,
  • Max operation frequency up to the reference clock frequency.

Device Tree

ecspi1: ecspi@02008000 {
  #address-cells = <1>;
  #size-cells = <0>;
  compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
  reg = <0x02008000 0x4000>;
  interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&clks IMX6UL_CLK_ECSPI1>,
           <&clks IMX6UL_CLK_ECSPI1>;
  clock-names = "ipg", "per";
  status = "disabled";
};

ecspi2: ecspi@0200c000 {
  [...]
};


          
        

        


                    
            
  •  litesom/devicetree/spi.txt
  •  Last modified: 2017/06/09 20:03
  • by filug